1. Field of the Invention
The present invention provides a method for making a mask, and more particularly, to a method of manufacturing a x 2.5 N+ polysilicon implantation mask, in which the x 2.5 N+ polysilicon implantation mask is made with a layout pattern generated by a logical operation.
2. Description of the Prior Art
Photolithography technology plays a critical role in processing of semiconductor wafers. Depending on the level of complexity in a circuit design, five to twenty photolithographic operations are required for each wafer. In a photolithographic process, the most important consideration is the design of the N polysilicon implantation mask. Since the circuit on a wafer is created with an N+ polysilicon implantation mask through a step-and-repeat exposure process, the selection and quality of the N+ polysilicon implantation will affect production yield and throughput.
Recently, to design and manufacture N+ polysilicon implantation masks, manufacturers would obtain a circuit layout data base provided by a client (normally an IC design house), including ion implantation layout data, N well layout data or salicide block (SAB) layout data, etc, and generate, with a computer aided designing (CAD) system, layout data meeting the design rules for wafer production.
According to the prior art, an N+ ion implantation process is performed by transferring the pattern of an N+ implantation mask onto the photoresist layer of a polysilicon layer. However, due to limitations in the photolithographic operation, x 2.5 N well ion implantation masks are ruled out for transferring layout patterns, as the line width is less than 0.25 micron. Instead, x 5 N well masks, which have a better resolution, are used. Due to this limitation, wafer production yield is limited.
To solve this problem, a x 2.5 P well mask is generally used for transferring the N ion implantation layout pattern onto a polysilicon layer. But when using x 2.5 P well mask for transferring the layout pattern, the following design rules must first be met: (1) N+ polysilicon resist devices must be placed within P well regions; and (2) P+ polysilicon resist devices must be placed within N well regions. Unfortunately, under some circumstances, the original layout data provided by a client might not comply with the two design rules; for this reason, a method has to be developed to accommodate these circumstances.
It is therefor a primary objective of this invention to provide a new method for manufacturing an implantation mask to correct the weaknesses described above.
The second objective of the invention is to provide a method for manufacturing x 2.5 N+ polysilicon implantation mask to improve the wafer production yield.
The third objective of the invention is to provide a method for manufacturing x 2.5 N+ polysilicon implantation mask which simultaneously determines the data of the N+ polysilicon implantation layout, the layout data of N+ polysilicon resist devices within N+ well regions, and the layout data of P+ polysilicon resist devices within P well regions.
Another objective of the invention is to provide a logical operation for making x 2.5 N+ polysilicon implantation mask.
In the present invention, an integrated circuit layout data base is first provided, which comprises N+ ion implantation layout data, P+ ion implantation layout data, defined polysilicon layout data, N well layout data, and SAB layout data. A logical operation is performed on this data base, the result of which includes the layout data of N+ polysilicon resist devices within the N well region, the layout data of the P+ polysilicon resist devices within the P well region, and the N well layout data, and which is used to make an N+ polysilicon implantation mask.
In the preferred embodiment according to this invention, the N+ polysilicon implantation mask is used to transfer the layout pattern onto a photoresist layer located on a polysilicon layer.
This invention utilizes the N+ implantation layout data to be processed on a polysilicon layer, the layout data of N+ polysilicon resist devices within N well region, and the layout data of P+ polysilicon resist devices within the N well region. Because of the application of the logical operation performed on the integrated circuit layout data in generating a new layout pattern, not only is the high production yield of a x 2.5 N+ implantation mask retained, but furthermore some original client circuit layout data, which does not comply with the design rules and was previously unusable, can be now be used.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.